Most oscillators required for silicon do not need crystal-level performance, but may still need a significant degree of accuracy. Typical oscillator designs often require an external resistor and/or capacitor to set a frequency. Unfortunately, even if accurately trimmed on-board components are used to maintain accuracy at high frequency, significant current consumption requirements may be required. Often, the best accuracy that can be achieved is 3% over an operating temperature range. Moreover, as will be understood by those skilled in the art, high frequency oscillators are particularly difficult to hold an accurate frequency unless they are locked to a known good reference, such as a crystal oscillator or resonator. But, these devices are typically implemented as off-chip components and may require significant amounts of power and add significantly to system cost. A typical implementation of a integrated circuit oscillator utilizes a high frequency voltage-controlled oscillator (VCO) divided down and compared to a known crystal oscillator (XO) or external resonator using a phase locked loop (PLL). Thus, a standard 10 MHz crystal could be used to generate a 32 MHz clock using a divider and a PLL. Other implementations can also require a large current (I) and/or large capacitance (C) to minimize the effects of parasitic variation with temperature. Unfortunately, high speed capacitors typically require large currents and the die area for such solutions can be substantial. Another example of an integrated circuit oscillator is disclosed in U.S. Pat. No. 4,904,960 to Izadinia et al., entitled “Precision CMOS Oscillator Circuit.”
As illustrated by FIG. 1A, a conventional frequency synthesizer 10 may include a fractional-N divider 12 within a feedback path of a phase-locked loop (PLL), which filters jitter in the output of the divider 12. This fractional-N divider 12 may operate by modulating between two or more integer values. The phase-locked loop of FIG. 1A contains a phase detector 14, which receives an input reference signal (e.g., 25 MHz), a charge pump 16, a loop filter 18 and a voltage-controlled oscillator (VCO) 20. This VCO 20 generates an output signal having a frequency that is a non-integer multiple of the frequency of the input reference signal. An integer divider 22 may also be provided for generating an output signal at a reduced frequency relative to the VCO output signal. Examples of the frequency synthesizer 10 of FIG. 1A are disclosed at U.S. Pat. No. 7,532,081 to Partridge et al., entitled “Frequency and/or Phase Compensated Microelectromechanical Oscillator,” and FIG. 3 of U.S. Pat. No. 7,417,510 to Huang, entitled “Direct Digital Interpolative Synthesis”.
FIG. 1B illustrates a frequency synthesizer 10′, which includes an integer divider 12′ within a feedback path of a phase-locked loop (PLL). This phase-locked loop contains a phase detector 14, which receives an input reference signal (e.g., 25 MHz), a charge pump 16, a loop filter 18 and a voltage-controlled oscillator (VCO) 20, which generates an output signal having a frequency that is an integer multiple of the frequency of the input reference signal. Multiple fractional-N dividers 22a-22d may be provided for generating output signals having different frequencies, which do not have integer relationships with the output frequency of the VCO 20. As will be understood by those skilled in the art, additional circuitry may be needed to reduce jitter in the signals generated by the dividers 22a-22d. The dividers 22a-22d may be provided as interpolative dividers as disclosed at FIGS. 4-6 of the '510 patent to Huang. For example, as shown by FIG. 5 of Huang, an interpolative divider can include a fractional-N divider, which receives a VCO clock. A first order delta sigma modulator receives a digital divide ratio (MIN). The integer portion of the digital divide ratio is supplied to the fractional-N divider as a divide control signal, which can be a stream of integers that approximate the fractional divide ratio. A digital quantization error, which corresponds to the fractional portion of the divide ratio, is supplied to a digitally controlled phase interpolator. The jitter introduced by the fractional-N divider can be canceled by interpolation in the phase interpolator, which is based on the digital quantization error supplied by the delta sigma modulator. In this manner, the input clock from the VCO is first divided down by the fractional-N divider according to the control information provided by the delta sigma modulator and then the phase interpolator operates to cancel quantization errors in the output of the fractional-N divider. Additional examples of fractional-N frequency synthesizers, which utilize an accumulator within a numerically-controlled oscillator and a phase interpolator, are disclosed at FIG. 6 of the '510 patent to Huang and in U.S. Pat. No. 7,724,097 to Carley et al., entitled “Direct Digital Synthesizer for Reference Frequency Generation.” A frequency synthesizer that utilizes segmented accumulators to support fractional division is disclosed in commonly assigned U.S. application Ser. No. 13/425,761 to Buell, entitled “Fractional-N Dividers Having Divider Modulation Circuits Therein With Segmented Accumulators,” the disclosure of which is hereby incorporated herein by reference.